`timescale 1ns/1ps

module tb_digital_tube();

reg sys_clk;
reg sys_rst_n;
wire [5:0]seg_sel;
wire [7:0]seg_led;

digital_tube #(
    .CNT_MAX(25_000)
) u_digital_tube (
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    .seg_sel(seg_sel),
    .seg_led(seg_led)
);
  
always #10 sys_clk = ~sys_clk;

initial begin
    sys_clk <= 1'b0;
    sys_rst_n <= 1'b0;
    #100
    sys_rst_n <= 1'b1;
end
endmodule